1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit having a decoding function and a level shifting function.
2. Description of Related Art
Conventionally, a so-called level shifter has been often used in combination with a decoder, in a level conversion circuit associated with a driver for a liquid crystal display or a fluorescent indicator tube.
Referring to FIG. 1, there is shown a typical conventional circuit having a two-input decoder, a level conversion circuit and a display driver. In the shown circuit, a logic circuit 10 has a high level corresponding to a ground potential and a low level corresponding to an ordinary power supply voltage. The logic circuit is connected to receive an enable signal 12 and a pair of input signals 14 and 16. The enable signal 12 is supplied to all four three-input NAND gates 18, 20, 22 and 24. A first input signal 14 is supplied directly to the NAND gates 20 and 24 and through an inverter 36 to the NAND gates 18 and 22, and a second input signal 16 is supplied directly to the NAND gates 22 and 24 and through an inverter 38 to the NAND gates 18 and 20.
Outputs of the NAND gates 18, 20, 22 and 24 are coupled to four inverters 40, 42, 44 and 46, respectively, which are also coupled at their output to four level shifters 48, 50, 52 and 54, respectively. Outputs of the level shifters 48, 50, 52 and 54 are connected to four drivers 56, 58, 60 and 62 for a liquid crystal display or a fluorescent indicator tube, respectively. In the above mentioned circuit, the four NAND gates 18 to 24 and the inverters 40 to 46 form a decoder 64.
With the above mentioned circuit, when the enable signal 12 is at a high level, one of the NAND gates 18 to 24 determined by the pair of input signals 14 and 16 is activated to generate a low level signal, which is inverted by the associated inverter so that a high level signal is supplied to the corresponding level shifter. On the other hand, the other three NAND gates are inactive, and therefore, generate a high level signal, which is inverted by the associated inverter so that a low level signal is applied to the corresponding level shifter.
However, when the enable signal 12 is at a low level, all of the NAND gates 18 to 24 are inactive to generate a high level signal, and therefore, low level signals generated by the associated inverters are supplied to all the level shifters 48 to 54, respectively.
Turning to FIG. 2, there is shown a circuit diagram of one typical example of a conventional level shifter. The shown level shifter includes a p-channel transistor 66 having a gate connected to receive an input signal 68 and a source connected to the ground, and another p-channel transistor 70 having a source connected to the ground and a gate connected to receive a signal 72 complementary to the input signal 68. A drain of the first p-channel transistor 66 is connected to a drain of an n-channel transistor 74 and a gate of another n-channel transistor 76, respectively. A drain of the second p-channel transistor 70 is connected to a drain of the second n-channel transistor 76 and a gate of the first n-channel transistor 74, respectively. Sources of the two n-channel transistors 74 and 76 are connected to a negative high potential V.sub.H which is different from the ordinary power supply voltage, and a connection node between the p-channel transistor 70 and the n-channel transistor 76 forms an output 78.
Now, if the input signal 68 is at a high level, the p-channel transistor 66 is off, and on the other hand, since the low level signal complementary to the input signal 68 is applied to the gate of the p-channel transistor 70, the p-channel transistor 70 is on. Accordingly, the gate of the n-channel transistor 74 is applied with a high level signal (corresponding to a level of the ground GND), so that the n-channel transistor 74 is turned on. On the other hand, the gate of the n-channel transistor 76 is applied with a low level signal (corresponding to a level of the high negative voltage V.sub.H), so that the n-channel transistor 76 is turned off. As a result, the high level signal corresponding to the ground level GND is supplied from the output 78.
Conversely, if the input signal 68 is at the low level, the p-channel transistor 66 is on, and the p-channel transistor 70 is off. Therefore, the n-channel transistor 74 is off and the n-channel transistor 76 is on. As a result, the low level signal corresponding to the level of the high negative voltage V.sub.H is supplied from the output 78.
The output signal 78 of the level shifter is applied to a driver for a liquid crystal display or a fluorescent indicator tube.
For example, in the circuit shown in FIG. 1, when the enable signal 12 is at the high level, if the input signals 14 and 16 are "0" and "0", respectively, the output jof only the three-input NAND gate 18 is activated so that the associated inverter 40 generates the high level signal to the corresponding level shifter 48. As a result, the level shifter 48 outputs the high level signal to the display driver 56. On the other hand, the other three-input NAND gates 20, 22 ad 24 are maintained inactive, and therefore, the inverters 42, 44 and 46 outputs the low level signals, so that the outputs of the corresponding level shifters 50, 52 and 54 are brought to the high negative voltage corresponding to the low level.
Thus, the signal having the high level corresponding to the ground level and the low level corresponding to the ordinary power supply voltage, is level-converted by the level shifter to the signal having the high level corresponding to the ground level and the low level corresponding to the negative high potential V.sub.H which is different from the ordinary power supply voltage.
The above mentioned level shifter operates to level-convert the decoded signal outputted from the decoder used in combination with the level shifter. If this circuit arrangement is formed in a semiconductor integrated circuit, the larger the number of input signals becomes, the larger the number of circuit elements becomes, and the larger the required layout area becomes. Accordingly, not only the design cost is increased, but also the manufacturing yield is decreased.